器件名称:
54ACT175F
功能描述:
Quad D Flip-Flop
文件大小:
141.62KB 共8页
简 介:
54AC175 54ACT175 Quad D Flip-Flop August 1998 54AC175 54ACT175 Quad D Flip-Flop General Description The ’AC/’ACT175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. n n n n n n Buffered positive edge-triggered clock Asynchronous common reset True and complement output Outputs source/sink 24 mA ’ACT175 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC175: 5962-89552 — ’ACT175: 5962-89693 Features n Edge-triggered D-type inputs Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100278-1 IEEE/IEC DS100278-3 Pin Assignment for LCC DS100278-2 Pin Names D0–D3 CP MR Q0–Q3 Q0–Q3 Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs DS100278-4 FACT is a registered trademark of Fairchild Semiconductor Corporation. 1998 National Semiconductor Corporation DS100278 www.national.com Functional Description The ’AC/’ACT175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock (CP) transition, causing individu……
