器件名称:
54LS114LMQB
功能描述:
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
文件大小:
118.08KB 共6页
简 介:
54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears June 1989 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description The ’LS114 features individual J K and set inputs and common clock and common clear inputs When the clock goes HIGH the inputs are enabled and data will be accepted The logic level of the J and K inputs may be allowed to change when the Clock Pulse is HIGH and the bistable will perform according to the truth table as long as the minimum setup times are observed Input data is transferred to the outputs on the negative-going edge of the clock pulse Connection Diagram Dual-In-Line Package Logic Symbol TL F 10176 – 1 Order Number 54LS114DMQB 54LS114FMQB or 54LS114LMQB See NS Package Number E20A J14A or W14B Pin Names J1 J2 K1 K2 CP CD SD1 SD2 Q1 Q2 Q1 Q2 Description TL F 10176 – 2 VCC e Pin 14 GND e Pin 7 Data Inputs Clock Pulse Input (Active Falling Edge) Direct Clear Input (Active LOW) Direct Set Inputs (Active LOW) Outputs C1995 National Semiconductor Corporation TL F 10176 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range b 55 C to a 125 C 54LS b 65 C to a 150 C Storage Temperature Range Recommended Operating Conditions Symbol VCC VIH VIL I……
