器件名称:
M12L128168A
功能描述:
2M x 16 Bit x 4 Banks Synchronous DRAM
文件大小:
786.32KB 共43页
简 介:
ESMT SDRAM M12L128168A 2M x 16 Bit x 4 Banks Synchronous DRAM ORDERING INFORMATION 54 Pin TSOP (Type II) (400mil x 875mil ) PRODUCT NO. M12L128168A-5TG M12L128168A-6TG M12L128168A-7TG MAX FREQ. PACKAGE COMMENTS 200MHz 166MHz 143MHz TSOP II TSOP II TSOP II Pb-free Pb-free Pb-free FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Pin Arrangement VDD DQ0 VDDQ DQ1 DQ2 V S SQ DQ3 DQ4 VDDQ DQ5 DQ6 V S SQ DQ7 VDD LDQM WE CAS RAS CS A13 A12 A10 /AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V S SQ DQ14 DQ13 VDDQ DQ12 DQ11 V S……
