器件名称:
M12L128324A
功能描述:
1M x 32 Bit x 4 Banks Synchronous DRAM
文件大小:
786.08KB 共47页
简 介:
ESMT Revision History Revision 0.1(May. 13 2005) -Original Revision 0.2 (Aug. 08 2005) -Delete Non-Pb-free of ordering information Revision 1.0 (Dec. 22 2005) -Delete “Preliminary” from datasheet -Add 90BGA Packing Dimension Revision 1.1 (Feb. 14 2006) -Modify ICC4, ICC5 spec Revision 1.2 (Mar. 14 2006) -Modify ICC2N, ICC3N spec M12L128324A Elite Semiconductor Memory Technology Inc. Publication Date: Mar. 2006 Revision: 1.2 1/47 ESMT SDRAM M12L128324A 1M x 32 Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (1, 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) ORDERING INFORMATION Product No. M12L128324A-6TG M12L128324A-7TG M12L128324A-6BG M12L128324A-7BG MAX FREQ. PACKAGE COMMENTS 166MHz 143MHz 166MHz 143MHz 86L TSOPII 86L TSOPII 90 FBGA 90 FBGA Pb-free Pb-free Pb-free Pb-free GENERAL DESCRIPTION The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be usefu……
