器件名称:
M12S128168A-10TG
功能描述:
2M x 16 Bit x 4 Banks Synchronous DRAM
文件大小:
960.01KB 共44页
简 介:
ESMT Revision History Revision 1.0 (Nov. 09, 2006) -Original M12S128168A Elite Semiconductor Memory Technology Inc. Publication Date: Nov. 2006 Revision: 1.0 1/44 ESMT SDRAM M12S128168A 2M x 16 Bit x 4 Banks Synchronous DRAM FEATURES ORDERING INFORMATION y y y y JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock Burst Read single write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) 54 Pin TSOP (Type II) (400mil x 875mil ) MAX FREQ. 100MHz PRODUCT NO. M12S128168A-10TG PACKAGE COMMENTS TSOP II Pb-free y y y y y GENERAL DESCRIPTION The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Pin Arrangement VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 4……
