器件名称:
M12S64322A-7BG
功能描述:
512K x 32 Bit x 4 Banks Synchronous DRAM
文件大小:
725.11KB 共46页
简 介:
ESMT Revision History Revision 1.0(May. 04 2007) -Original M12S64322A Elite Semiconductor Memory Technology Inc. Publication Date: May. 2007 Revision: 1.0 1/46 ESMT SDRAM M12S64322A 512K x 32 Bit x 4 Banks Synchronous DRAM FEATURES y y y y JEDEC standard 2.5V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 15.6μs refresh interval ORDERING INFORMATION Product No. M12S64322A-6TG M12S64322A-7TG M12S64322A-6BG M12S64322A-7BG MAX FREQ. PACKAGE COMMENTS 166MHz 143MHz 166MHz 143MHz TSOPII TSOPII 90BGA 90BGA Pb-free Pb-free Pb-free Pb-free y y y y GENERAL DESCRIPTION The M12S64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN ARRANGEMENT Top View VDD DQ0 VDD Q DQ1 DQ2 VSSQ DQ3 DQ4 VDD Q DQ5 DQ6 VS S Q DQ7 NC VDD DQ M 0 WE CA S RA S CS NC BA0 BA1 A10/AP A0 A1 A2 D QM 2 VDD NC DQ 16 VSS Q DQ 17 DQ 18 VDD Q DQ 19 DQ 20 VSS Q……
