器件名称:
M13S64164A-5BG
功能描述:
1M x 16 Bit x 4 Banks Double Data Rate SDRAM
文件大小:
1506.5KB 共49页
简 介:
ESMT Revision History Revision 0.1 (23 Oct. 2006) - Original Revision 0.2 (06 Jun. 2007) - Add BGA type spec Revision 0.3 (20 Jul. 2007) - Modify BGA assignment Preliminary M13S64164A Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 0.3 1/49 ESMT DDR SDRAM Features z z z z z z z z z z z z z z z z z z z Preliminary M13S64164A 1M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 2.5, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for reads; center-aligned with data for WRITE Data mask (DM) for write masking only For 2.5V parts, VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.7V Auto & Self refresh 64ms refresh period, 4K cycle SSTL-2 I/O interface 66pin TSOPII package Ordering information : PRODUCT NO. M13S64164A -5TG M13S64164A -6TG M13S64164A -5BG M13S64164A -6BG MAX FREQ 200MHz 166MHz 200MHz 166MHz 2.5V BGA VDD 2.5V PACKAGE 66TSOPII COMMENTS Pb-free Pb-free Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 0.3 2/49 ESMT Functional Block Diagram CLK CLK CKE Address……
