器件名称:
M52D128168A-10BG
功能描述:
2M x 16 Bit x 4 Banks Synchronous DRAM
文件大小:
1188.06KB 共47页
简 介:
ESMT Revision History Revision 1.0 (May. 29, 2007) -Original Preliminary M52D128168A Elite Semiconductor Memory Technology Inc. Publication Date: May. 2007 Revision: 1.0 1/47 ESMT SDRAM FEATURES y y y y Preliminary M52D128168A 2M x 16 Bit x 4 Banks Synchronous DRAM MAX FREQ. y y y y y y 1.8V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) EMRS cycle with address All inputs are sampled at the positive going edge of the system clock Special function support - PASR (Partial Array Self Refresh) - TCSR (Temperature Compensated Self Refresh) - DS (Driver Strength) DQM for masking Auto & self refresh 64ms refresh period (4K cycle) PRODUCT NO. PACKAGE 54 TSOP II 54 Ball FBGA 54 TSOP II 54 Ball FBGA Comments Pb-free Pb-free Pb-free Pb-free M52D128168A-7.5TG 133MHz M52D128168A-7.5BG 133MHz M52D128168A-10TG M52D128168A-10BG 100MHz 100MHz ORDERING INFORMATION GENERAL DESCRIPTION The M52D128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system appl……
