器件名称:
M74HC194
功能描述:
4 BIT PIPO SHIFT REGISTER
文件大小:
271.78KB 共12页
简 介:
M54HC194 M74HC194 4 BIT PIPO SHIFT REGISTER . . . . . . . . HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS194 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC194F1R M74HC194M1R M74HC194B1R M74HC194C1R DESCRIPTION The M54/74HC194 is a high speed CMOS 4 BIT PIPO 2 SHIFT REGISTER fabricated in silicon gate C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This SHIFT REGISTER is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, clear line. The register has four distinct modes of operation : PARALLEL (broadside) LOAD ; SHIFT RIGHT (in the direction QA QD); SHIFT LEFT ; INHIBIT CLOCK (do nothing). Synchronous parallel loading is accomplished by applying the four data bits and taking both mode control inputs, S0 and S1 high. The data are loaded into their respective flip-flops and appear at the outputs after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift ……
