器件名称:
M74HC77
功能描述:
4-BIT D-TYPE LATCH
文件大小:
241.66KB 共10页
简 介:
M74HC77 4 BIT D TYPE LATCH s s s s s s s HIGH SPEED : tPD = 11 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 77 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC77B1R M74HC77M1R T&R M74HC77RM13TR M74HC77TTR DESCRIPTION The M74HC77 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. It contains two groups of 2 bit latches controlled by an enable input (G12 or G34). These two latch groups can be used in different circuits. The data applied to the data inputs (1D, 2D, or 3D, 4D) are transferred to the Q outputs (1Q, 2Q, or 3Q, 4Q) respectively when the enable input (G12 or G34) is taken high. The Q outputs will follow the data inputs as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data input is retained at the Q outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/10 M74HC77 IINPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 5, 6 3 7, 10 8, 9, 13, 14 12 11 4 SYMBOL 1D to 4D G3 4 NC 1Q to 4Q G1 2 GND VCC NAME AND FUNCTION Data Inputs Latch Enable Input, Latches 3 and 4……
