器件名称:
74273
功能描述:
Octal D Flip-Flop with Common Clock and Reset
文件大小:
250.59KB 共7页
简 介:
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC54/74HC273A is identical in pinout to the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip–flops with common Clock and Reset inputs. Each flip–flop is loaded with a low–to–high transition of the Clock input. Reset is asynchronous and active low. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 264 FETs or 66 Equivalent Gates MC54/74HC273A J SUFFIX CERAMIC PACKAGE CASE 732–03 1 20 20 1 N SUFFIX PLASTIC PACKAGE CASE 738–03 DW SUFFIX SOIC PACKAGE CASE 751D–04 DT SUFFIX TSSOP PACKAGE CASE 948E–02 20 1 20 1 ORDERING INFORMATION LOGIC DIAGRAM 3 4 7 8 13 14 17 18 19 11 2 5 6 9 12 15 16 MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS Ceramic Plastic SOIC TSSOP D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK PIN ASSIGNMENT RESET Q0 D0 D1 Q1 Q2 D2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CLOCK RESET PIN 20 = VCC PIN 10 = GND Design Criteria Value 66 Units ea ns Internal Gate Count* Int……
