器件名称:
74FR1074SC
功能描述:
Dual D-Type Flip-Flop
文件大小:
66.93KB 共8页
简 介:
74FR74 74FR1074 Dual D-Type Flip-Flop March 1992 Revised August 1999 74FR74 74FR1074 Dual D-Type Flip-Flop General Description The 74FR74 and 74FR1074 are dual D-type flip-flops with true and complement (Q/Q) outputs. On the 74FR74, data at the D inputs is transferred to the outputs on the rising edge of the clock input (CPn). The 74FR1074 is the negative edge triggered version of this device. Both parts feature asynchronous clear (CDn) and set (SDn) inputs which are low level enabled. Features s 74FR74 is pin-for-pin compatible with the 74F74 s True 150 MHz fMAX capability on 74FR74 s Outputs sink 24 mA and source 24 mA s Guaranteed pin-to-pin skew specifications Ordering Code: Order Number 74FR74SC 74FR74PC 74FR1074SC 74FR1074PC Package Number M14A N14A M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74FR74 74FR1074 1999 Fairchild Semiconductor Corporation DS010977 www.fairchildsemi.com 74FR74 74FR1074 Logic Symbols 74FR74 Pin Descriptions Pin Names Dn CPn SDn CDn Qn Qn Data Inputs Clock Inputs Asynchronous Set Inputs Asynchronous Clear Inputs True Output Complemen……
