器件名称:
74HC160N
功能描述:
Presettable synchronous BCD decade counter; asynchronous reset
文件大小:
63.72KB 共9页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT160 Presettable synchronous BCD decade counter; asynchronous reset Product specication File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specication Presettable synchronous BCD decade counter; asynchronous reset FEATURES Synchronous counting and loading Two count enable inputs for n-bit cascading Positive-edge triggered clock Asynchronous reset Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable QUICK REFERENCE DATA GND = 0 V; Tamb= 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC propagation delay CP to Qn CP to TC CET to TC maximum clock frequency input capa……
