器件名称:
74HC273D
功能描述:
Octal D-type flip-flop with reset; positive-edge trigger
文件大小:
58.4KB 共8页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT273 Octal D-type flip-flop with reset; positive-edge trigger Product specication File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specication Octal D-type ip-op with reset; positive-edge trigger FEATURES Ideal buffer for MOS microprocessor or memory Common clock and master reset Eight positive edge-triggered D-type flip-flops See “377” for clock enable version See “373” for transparent latch version See “374” for 3-state version Output capability; standard ICC category: MSI GENERAL DESCRIPTION 74HC/HCT273 The 74HC/HCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the t……
