器件名称:
74HC3G34DP
功能描述:
Triple Buffer Gate
文件大小:
81.81KB 共16页
简 介:
INTEGRATED CIRCUITS DATA SHEET 74HC3G34; 74HCT3G34 Triple buffer gate Product specication Supersedes data of 2003 Feb 10 2003 May 19 Philips Semiconductors Product specication Triple buffer gate FEATURES Wide supply voltage range from 2.0 to 6.0 V Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Very small 8-pin package Output capability: standard ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns. DESCRIPTION 74HC3G34; 74HCT3G34 The 74HC3G/HCT3G34 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). Specified in compliance with JEDEC standard no. 7. The 74HC3G/HCT3G34 provides three buffers. TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. 2. For 74HC3G34 the condition is VI = GND to VCC. For 74HCT3G34 the condition is VI = GND to VCC 1.5 V. FUNCTION TABLE See note 1. INPUT nA L H Note 1. H = HIGH voltage level; L = LOW voltage level. 2003 May 19 2 OUTPUT nY L H PARAMETER propagation delay nA to nY input capacitance power dissipation capacitance per gate notes 1 and……
