器件名称:
74HC4020D
功能描述:
14-stage binary ripple counter
文件大小:
49.93KB 共7页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4020 14-stage binary ripple counter Product specication File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specication 14-stage binary ripple counter FEATURES Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the “4020” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT4020 The 74HC/HCT4020 are 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0, Q3 to Q13). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Q0 Qn to Qn+1 MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capa……
