器件名称:
74HC4046
功能描述:
Phase-Locked Loop
文件大小:
134.42KB 共12页
简 介:
SL74HC4046 Phase-Locked Loop High-Performance Silicon-Gate CMOS The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC4046 phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain opamp DEM OUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1OUT and maintains 90 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 50% duty cycle). Phase comparator 2 ORDERING INFORMATION (with leading-edge sensing logic) provides digital error signals PC2OUT SL74HC4046N Plastic and PCPOUT and maintains a 0 degree phase shift between SIGIN and SL74HC4046D SOIC COMPIN signals (duty cycle is immaterial). The linear VCO produces an TA = -55° to 125° C for all packages output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEM OUT with an external resistor is used where the VCOIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the V……
