器件名称:
74HC4516
功能描述:
Binary up/down counter
文件大小:
100.19KB 共14页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4516 Binary up/down counter Product specication File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specication Binary up/down counter FEATURES Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4516 are high-speed Si-gate CMOS devices and are pin compatible with the “4516” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4516 are edge-triggered synchronous up/down 4-bit binary counters with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH Logic equation for terminal count: TC = CE . {(UP/DN) . Q 0 . Q 1 . Q 2 . Q 3 + (UP DN ) . Q 0 . Q 1 . Q 2 . Q 3 } QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT4516 parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. When PL and CE are LOW, the counter changes on the LOW-to-HIGH transition of CP. ……
