器件名称:
74HC58DB
功能描述:
Dual AND-OR gate
文件大小:
35.92KB 共5页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC58 Dual AND-OR gate Product specication File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specication Dual AND-OR gate FEATURES Output capability: standard ICC category: SSI GENERAL DESCRIPTION 74HC58 The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate. QUICK REFERENCE DATA GND = 0 V; Tamb = 15 °C; tr = tf = 6 ns SYMBOL tPHL/ tPLH PARAMETER propagation delay 1n to 1Y 2n to 2Y CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V ∑ (CL × VCC2 × fo) = sum of outputs 2. For HC the condition is VI = GND to VCC ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS CL = 15 pF; VCC = 5 V 11 9 3.5 18 ns ns pF pF TYPICAL……
