器件名称:
74HC74PW
功能描述:
Dual D-type flip-flop with set and reset; positive-edge trigger
文件大小:
120.16KB 共22页
简 介:
INTEGRATED CIRCUITS DATA SHEET 74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specication Supersedes data of 1998 Feb 23 2003 Jul 10 Philips Semiconductors Product specication Dual D-type ip-op with set and reset; positive-edge trigger FEATURES Wide supply voltage range from 2.0 to 6.0 V Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. 74HC74; 74HCT74 GENERAL DESCRIPTION The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nCP to nQ, nQ nSD to nQ……
