器件名称:
74HCT40103N
功能描述:
8-bit synchronous binary down counter
文件大小:
136.67KB 共17页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT40103 8-bit synchronous binary down counter Product specication Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jul 08 Philips Semiconductors Product specication 8-bit synchronous binary down counter FEATURES Cascadable Synchronous or asynchronous preset Output capability: standard ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the “40103” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The “40103” contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT40103 Counting is inhibited when the terminal enable input (TE) is HIGH. The te……
