器件名称:
74HCT7731
功能描述:
Quad 64-bit static shift register
文件大小:
49.35KB 共8页
简 介:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7731 Quad 64-bit static shift register Product specication File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specication Quad 64-bit static shift register FEATURES Frequency range DC to 100 MHz. Separate serial data inputs Cascadable Functionally compatible with HEF 4731 Includes recycling mode Direct shift out Output capability: Standard ICC category: LSI. APPLICATIONS Data storage Delay line. GENERAL DESCRIPTION The HC/HCT7731 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no. 7A. The HC/HCT7731 are quad 64-bit static shift registers with a recycling mode. Each register has separate data inputs Da to Dd, clock inputs CPa to CPd and data outputs Qa to Qd. Data shifts one place towards the output, each LOW to HIGH transition of the clock pulse. Each recycling mode input controls two registers RECab for registers A and B and RECcd for registers C and D. When the REC input is HIGH, the device is in the recycling mode and data at the output is shifted back into the input of the register, so after 64 clock pulses the contents of a register is again in its original position. This enables the user to tap off data from any position. When the REC……
