器件名称:
74LV4040PW
功能描述:
12-stage binary ripple counter
文件大小:
133.75KB 共14页
简 介:
INTEGRATED CIRCUITS 74LV4040 12-stage binary ripple counter Product specification IC24 Data Handbook 1998 Jun 23 Philips Semiconductors Philips Semiconductors Product specification 12-stage binary ripple counter 74LV4040 FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, Frequency dividing circuits Time delay circuits Control counters Output capability: standard ICC category: MSI QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL PARAMETER Propagation delay CP to Q0 Qn to Qn+1 MR to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per gate Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV4040 is a low–voltage Si–gate CMOS device and is pin and function compatible with 74HC/HCT4040. The 74LV4040 is a 12-stage binary ripple counter with a click input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0 to Q11). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. CONDITIONS CL = 15pF VCC = 3.3V TYPICAL 12 7 16 100 3.5 UNIT tPHL/tPLH fmax CI CPD ns MHz pF pF Notes 1 and 2 30 NOTES: 1. CPD is used to determine the dynamic power dissipa……
