器件名称:
74LV4066DB
功能描述:
Quad bilateral switches
文件大小:
84.2KB 共10页
简 介:
INTEGRATED CIRCUITS 74LV4066 Quad bilateral switches Product specification Supersedes data of 1996 Jan 01 IC24 Data Handbook 1998 Jun 23 Philips Semiconductors Philips Semiconductors Product specification Quad bilateral switches 74LV4066 FEATURES Optimized for Low Voltage applications: 1.0V to 6.0V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Tamb = 25 °C. Very low typ “ON” resistance: 25W at VCC – VEE = 4.5 V 35W at VCC – VEE = 3.0 V 60W at VCC – VEE = 2.0 V The 74LV4066 has four independent analog switches. Each switch has two input/output terminals (nY, nZ) and an active HIGH enable input (nE). When nE is LOW the corresponding analog switch is turned off. The 74LV4066 has an on resistance which is dramatically reduced in comparison with 74HCT4066. FUNCTION TABLE INPUTS nE L H NOTES: H = HIGH voltage level L = LOW voltage level SWITCH off on Output capability: non-standard ICC category: SSI DESCRIPTION The 74LV4066 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT4066. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf v 2.5 ns SYMBOL tPZH/tPZL tPHZ/tPLZ CI CPD CS PARAMETER Turn “ON” time: nE to VOS Turn “OFF” time: nE to VOS Input capacitance Power dissipation capacitance per switch Maximum switch capacitances Notes 1, 2 CONDITIONS CL = 15pF RL = 1KW VCC= 3.3V TYPICAL 10 13 3.5 11 8 UNIT ns ns pF pF pF NOTES: 1. CPD is used to determine the ……
