器件名称: M74HC4024C1R
功能描述: 7 STAGE BINARY COUNTER
文件大小: 246.62KB 共11页
简 介:M54HC4024 M74HC4024
7 STAGE BINARY COUNTER
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HIGH SPEED tPD = 13 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25° C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH|= IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 4024B
B1R (Plastic Package)
F1R (Ceramic Package)
M1R (Micro Package)
C1R (Chip Carrier)
ORDER CODES : M54HC4024F1R M74HC4024M1R M74HC4024B1R M74HC4024C1R
PIN CONNECTIONS (top view)
DESCRIPTION The M54/74HC4024 is a high speed CMOS 7STAGE BINARY COUNTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The HC4024 is a 7 stage Counter. This devices is incremented on the falling edge (negative transition) of the input clock, and all its outputs are reset to a low level by applying a logical high on their reset input. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
October 1992
NC = No Internal Connection
1/11
M54/M74HC4024
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
CLOCK X CLEAR H L L
X: DON’T CARE
OUTPUT STATE ALL OUTPUTS = ”L” NO CHANGE ADVANCE TO NEXT STATE
LOGIC DIAGRAM
2/11
M54/ M74HC4024
PIN DESCRIPTION
PIN No 1 2 12, 11, 9, 6, 5, 4, 3 8, 10, 13 7 14 SYMBOL CLOCK RESET Q1 to Q7 NC GND V CC ……
