器件名称:
M74HC4024RM13TR
功能描述:
7 STAGE BINARY COUNTER
文件大小:
322.05KB 共10页
简 介:
M74HC4024 7 STAGE BINARY COUNTER s s s s s s s HIGH SPEED : fMAX = 79 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 4024 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC4024B1R M74HC4024M1R T&R M74HC4024RM13TR M74HC4024TTR DESCRIPTION The M74HC4024 is an high speed CMOS 7 STAGE BINARY COUNTER fabricated with silicon gate C2MOS technology. This devices is incremented on the falling edge (negative transition) of the input clock, and all its outputs are reset to a low level by applying a logical high level on their reset input (CLEAR). All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/10 M74HC4024 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2 12, 11, 9, 6, 5, 4, 3 8, 10, 13 7 14 SYMBOL CLOCK CLEAR Q1 to Q7 NC GND Vcc NAME AND FUNCTION Clock Input (HIGH to LOW, Edge-triggered) Reser Input (Active High) Parallel Inputs Not Connected Ground (0V) Positive Supply Voltage TRUTH TABLE CLOCK X CLEAR H L L OUTPUT STATE ALL OUTPUTS = "L" NO CHANGE ADVANCE TO NEXT STATE LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol ……
