器件名称:
MC74HC4024D
功能描述:
7-Stage Binary Ripple Counter
文件大小:
173.21KB 共6页
简 介:
MOTOROLA SEMICONDUCTOR TECHNICAL DATA 7-Stage Binary Ripple Counter High–Performance Silicon–Gate CMOS The MC74HC4024 is identical in pinout to the standard CMOS MC14024. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 7 master–slave flip–flops. The output of each flip–flop feeds the next and the frequency at each output is half that of the preceding one. The state of the counter advances on the negative going edge of the Clock input. Reset is asynchronous and active–high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4024 for some designs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 206 FETs or 51.5 Equivalent Gates 14 MC74HC4024 N SUFFIX PLASTIC PACKAGE CASE 646–06 1 14 1 D SUFFIX SOIC PACKAGE CASE 751A–03 ORDERING INFORMATION MC74HCXXXXN MC74HCXXXXD Plastic SOIC PIN ASSIGNMENT CLOCK RESET Q7 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC NC Q1 Q2 NC Q3 NC LOGIC DIAGRAM 12 11 9 CLOCK 1 6 5 4 3 RESET 2 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Clock Q6 Q5 Q4 GND NC = NO CONNECTION FUNCTION TABLE……
