器件名称:
M74HC280M1R
功能描述:
9 BIT PARITY GENERATOR
文件大小:
242.33KB 共10页
简 介:
M54HC280 M74HC280 9 BIT PARITY GENERATOR . . . . . . . . HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) at TA = 25 °C 6 V HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS280 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC280F1R M74HC280M1R M74HC280B1R M74HC280C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. It is composed of nine data inputs (A to I) and odd/even parity outputs (Σ ODD and Σ EVEN). The nine data inputs control the output conditions. When the number of high level inputs is odd, ΣODD output is kept high and ΣEVEN output low. Conversely, when the number is even , ΣEVEN output is kept high and ΣODD low. This IC generates either odd or even parity making it flexible application. The word-length capability is easily expanded by cascading. All inputs are equipped with protection circuits against static discharge and transient excess voltage. October 1992 NC = No Internal Connection 1/10 M54/M74HC280 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE NUMBER OF IN……
