器件名称:
CD54HC259_06
功能描述:
High-Speed CMOS Logic 8-Bit Addressable Latch
文件大小:
278.39KB 共14页
简 介:
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Data sheet acquired from Harris Semiconductor SCHS173C November 1997 - Revised October 2003 High-Speed CMOS Logic 8-Bit Addressable Latch Description The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky. This latches three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR and LE are high (Memory Mode), all outputs are isolated from the Data input, i.e., all latches hold the last data presented before the LE transition from low to high. A condition of LE low and MR high (Addressable Latch mode) allows the addressed latch’s output to follow the data input; all other latches are unaffected. The Reset mode (all outputs low) results when LE is high and MR is low. Features Buffered Inputs and Outputs [ /Title (CD74 HC259 , CD74 HCT25 9) /Subject (High Speed CMOS Logic 8-Bit Addres sable Latch) Four Operating Modes Typical Propagation Delay of 15ns at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signi……
