器件名称:
CD54HCT299
功能描述:
High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
文件大小:
431.93KB 共17页
简 介:
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 Data sheet acquired from Harris Semiconductor SCHS178C January 1998 - Revised May 2003 High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State Description The ’HC259 and ’HCT299 are 8-bit shift/storage registers with three-state bus interface capability. The register has four synchronous-operating modes controlled by the two select inputs as shown in the mode select (S0, S1) table. The mode select, the serial data (DS0, DS7) and the parallel data (I/O0 - I/O7) respond only to the low-to-high transition of the clock (CP) pulse. S0, S1 and data inputs must be stable one setup time prior to the clock positive transition. The Master Reset (MR) is an asynchronous active low input. When MR output is low, the register is cleared regardless of the status of all other inputs. The register can be expanded by cascading same units by tying the serial output (Q0) to the serial data (DS7) input of the preceding register, and tying the serial output (Q7) to the serial data (DS0) input of the following register. Recirculating the (n x 8) bits is accomplished by tying the Q7 of the last stage to the DS0 of the rst stage. The three-state input/output I(/O) port has three modes of operation: 1. Both output enable (OE1 and OE2) inputs are low and S0 or S1 or both are low, the data in the register is presented at the eight outputs. 2. When both S0 and S1 are high, I/O terminals are in the high impedance state but being input ports, ready fo……
