器件名称:
M74HC166B1R
功能描述:
8 BIT PISO SHIFT REGISTER
文件大小:
270.3KB 共13页
简 介:
M54HC166 M74HC166 8 BIT PISO SHIFT REGISTER . . . . . . . . HIGH SPEED fMAX = 57 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS166 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC166F1R M74HC166M1R M74HC166B1R M74HC166C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC166 is a high speed C2MOS 8 BIT PISO SHIFT REGISTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. It consists of parallel or serial inputs and a serial-out 8-bit shift register with gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are controlled by the SHIFT/LOAD input. When the SHIFT/LOAD input is held high, the serial data input is enabled and the eight flip-flops perform serial shifting with each clock pulse. When held low, the parallel data inputs are enabled and synchronous loading occurs on the next clock pulse. Clocking is accomplished on the low-to-high level edge of the clock pulse. The CLOCK-INHIBIT input should be changed to the high only while the CLOCK input is held high. A direct clear input overrides all……
