器件名称:
M74HC195M1R
功能描述:
8 BIT PIPO SHIFT REGISTER
文件大小:
264.08KB 共13页
简 介:
M54HC195 M74HC195 8 BIT PIPO SHIFT REGISTER . . . . . . . . HIGH SPEED tPD = 13 ns (TYP.) at VCC = 5 V LOW POWER DISSIPATION ICC = 4 A (MAX.) at TA = 25 °C 6 V HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V to 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS195 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC195F1R M74HC195M1R M74HC195B1R M74HC195C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC195 is a high speed CMOS 4 BIT PIPO SHIFT REGISTER fabricated in silicon gate 2 C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. This shift register features parallel inputs, parallel outputs, J-K serial inputs, a SHIFT/LOAD control input, and a direct overriding CLEAR. This shift register can operate in two modes : Parallel Load ; Shift from QA towards QD. Parallel loading is accomplished by applying the four bits of data, and taking the SHIFT/LOAD control input low. The data is loaded into the associated flip flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the SHIFT/LOAD control input is high. Serial data for this mode is entered at the J-K inputs. T……
