器件名称:
M74HC259M1R
功能描述:
8 BIT ADDRESSABLE LATCH
文件大小:
557.59KB 共13页
简 介:
M74HC259 8 BIT ADDRESSABLE LATCH s s s s s s s HIGH SPEED : tPD = 20 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 259 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC259B1R M74HC259M1R T&R M74HC259RM13TR M74HC259TTR DESCRIPTION The M74HC259 is an high speed CMOS 8 BIT ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. The M74HC259 has single data input (D) 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), common enable input (E), and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B, and C inputs. When ENABLE is taken low the data flows through to the addresses output. The data is stored on the positive-going edge of the ENABLE pulse. All unaddressed latches will remain unaffected. With ENABLE in the high state the device is deselected and all PIN CONNECTION AND IEC LOGIC SYMBOLS latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the ENABLE should be held high (inactive) while the address lines are changing. If ENABLE is held ……
