ADP1046：隔离DC-DC副边应用控制器应用详解（独家）

控制理论

电流检测

The ADP1046 has two current sense inputs: CS1 and CS2±. These inputs sense, protect, and control the primary input current, secondary output current, and the share bus information. They can be calibrated to reduce errors due to external components.

CS1操作(CS1)

CS1 is typically used for the monitoring and protection of the primary side current, which is commonly sensed using a current transformer (CT). The input signal at the CS1 pin is fed into an ADC for current monitoring. The range of the ADC is 0 V to 1.4 V. The input signal is also fed into a comparator for pulse-by-pulse OCP protection. The typical configuration for the CS1 current sense is shown in Figure 1.

Figure 1

The CS1 ADC is used to measure the average value of the primary current; the reading is averaged every 2.62 ms in an asynchronous fashion to make fault decisions. The ADP1046 also writes the 12-bit CS1 reading every 10 ms to Register 0x13.

The fast OCP comparator is used to limit the instantaneous primary current within each switching cycle and has a nominal threshold of 1.2 V.Various thresholds and limits can be set for CS1, as described in the Current Sense and Current Limit Registers section.

CS2 操作(CS2+, CS2−)

CS2+ and CS2− are differential inputs used for the monitoring and protection of the secondary side current. The full-scale range of the CS2 ADC is programmable to 60 mV or 120 mV. The differential inputs are fed into an ADC through a pair of external resistors that provide the necessary level shifting. The device pins, CS2+ and CS2−, are internally regulated to approxi-mately 1 V by internal current sources.

When using low-side current sensing, the current sources are 200 μA; therefore, the required resistor value is 1 V/200 μA = 5 kΩ. When using high-side current sensing, the current sources are 2 mA; therefore, the resistor value required is (VOUT − 1 V)/2 mA. In the case of VOUT = 12 V, the required resistor value is 5.5 kΩ.

Typical configurations are shown in Figure 2 and Figure 3. Various thresholds and limits can be set for CS2±, such as OCP. These thresholds and limits are described in the Current Sense and Current Limit Registers section.

Figure 2

Figure 3

When not in use, the CS2+ and CS2− inputs should both be connected directly to PGND, and CS2± should be set to high-side current sense mode (Register 0x27[2] = 1).

The CS2 ADC is used to measure the CS2 current; the reading is averaged every 2.62 ms in an asynchronous fashion. This averaged reading is used to make fault decisions, such as the CS2 OCP fault. The ADP1046 also writes the 12-bit CS2 reading every 10 ms to Register 0x18.

电压检测

Multiple voltage sense inputs on the ADP1046 are used for the monitoring, control, and protection of the power supply output. This information is available through the I2C interface. All voltage sense points can be calibrated digitally to minimize errors due to external components. This calibration can be performed in the production environment, and the settings can be stored in the EEPROM of the ADP1046 (see the Power Supply Calibration and Trim section for more information).

For voltage monitoring, the VS1, VS2, and VS3 voltage value registers (Register 0x15, Register 0x16, and Register 0x17, respectively) are updated every 10 ms. The ADP1046 stores every ADC sample for 10 ms and then outputs the average value at the end of the 10 ms period. Therefore, if these registers are read at least every 10 ms, a true average value is read.

The ADP1046 uses two separate sensing points: VS1 and VS3±, depending on the condition of the OrFET. When the OrFET is turned off, the control loop is regulated via VS1; when the OrFET is turned on, the control loop is regulated via the differential sensing on VS3±. This sensing mechanism effectively performs a local and remote voltage sense.

The control loop of the ADP1046 features a patented multipath architecture. The output voltage is converted simultaneously by two ADCs: a high accuracy ADC and a high speed ADC. The complete signal is reconstructed and processed in the digital filter to provide a high performance, cost competitive solution.

模数转换器

Two kinds of Σ-Δ ADCs are used in the feedback loop of the ADP1046: a low frequency (LF) ADC that runs at 1.56 MHz and a high frequency (HF) ADC that runs at 25 MHz.

Σ-Δ ADCs have a resolution of one bit and operate differently from traditional flash ADCs. The equivalent resolution obtain-able depends on how long the output bit stream of the Σ-Δ is sampled.

Σ-Δ ADCs also differ from Nyquist rate ADCs in that the quan-tization noise is not uniform across the frequency spectrum. At lower frequencies, the noise is lower, and at higher frequencies, the noise is higher (see Figure 4).

Figure 4

The low frequency ADC runs at approximately 1.56 MHz. For a specified bandwidth, the equivalent resolution can be calculated as follows:

ln(1.56 MHz/BW)/ln2 =Nbits

For example, at a bandwidth of 95 Hz, the equivalent resolution/noise is

ln(1.5 MHz/95)/ln2 = 14 bits

At a bandwidth of 1.5 kHz, the equivalent resolution/noise is

ln(1.56 MHz/1.5 kHz)/ln2 = 10 bits

The high frequency ADC has a clock of 25 MHz. It is comb filtered and outputs at the switching frequency (fSW) into the digital filter. The equivalent resolution at some sample frequencies is listed in Table 5.

Figure 5

The HF ADC has a range of ±30 mV. Using a base switching frequency (fSW) of 100 kHz (8-bit HF ADC resolution), when fSW increases to 200 kHz (7-bit HF ADC resolution), the quantization noise is 0.9375 mV (1 LSB). Increasing fSW to 400 kHz increases the quantization noise to 3.75 mV (1 LSB = 2 × 30 mV/26 = 0.9375 mV).

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ADP1046：隔离DC-DC副边应用控制器快速入门指南