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FPGA实验连载(二、数码管1)

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2012-10-12 23:23:38 打赏

-- 7段数码管实验2:递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001….
-- 设计了一个4位十进制计数器,并用数码管显示当前计数值

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY seg1 IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
dataout : OUT std_logic_vector(7 DOWNTO 0); --各段数据输出
en : OUT std_logic_vector(3 DOWNTO 0)); --COM使能输出
END seg1;

ARCHITECTURE arch OF seg1 IS
signal div_cnt : std_logic_vector(24 downto 0 );
signal data4 : std_logic_vector(3 downto 0);
signal dataout_xhdl1 : std_logic_vector(7 downto 0);
signal en_xhdl : std_logic_vector(3 downto 0);
signal cntfirst :std_logic_vector(3 downto 0);
signal cntsecond : std_logic_vector(3 downto 0);
signal cntthird : std_logic_vector(3 downto 0);
signal cntlast : std_logic_vector(3 downto 0);
signal first_over: std_logic;
signal second_over: std_logic;
signal third_over : std_Logic;
signal last_over : std_logic;
begin

dataout<=dataout_xhdl1;
en<=en_xhdl;

process(clk,rst)
begin
if(rst='0')then
div_cnt<="0000000000000000000000000";
elsif(clk'event and clk='1')then
div_cnt<=div_cnt+1;
end if;
end process;

process(div_cnt(24),rst,last_over) ---first 10 counter
begin
if(rst='0')then
cntfirst<="0000";
first_over<='0';
elsif(div_cnt(24)'event and div_cnt(24)='1')then
if(cntfirst="1001" or last_over='1')then
cntfirst<="0000";
first_over<='1';
else
first_over<='0';
cntfirst<=cntfirst+1;
end if;
end if;
end process;


process(first_over,rst) --second 10 counter
begin
if(rst='0')then
cntsecond<="0000";
second_over<='0';
elsif(first_over'event and first_over='1')then
if(cntsecond="1001")then
cntsecond<="0000";
second_over<='1';
else
second_over<='0';
cntsecond<=cntsecond+1;
end if;
end if;
end process;


process(second_over,rst) --second 10 counter
begin
if(rst='0')then
cntthird<="0000";
third_over<='0';
elsif(second_over'event and second_over='1')then
if( cntthird="1001")then
cntthird<="0000";
third_over<='1';
else
third_over<='0';
cntthird<= cntthird+1;
end if;
end if;
end process;

process(third_over,rst) --second 10 counter
begin
if(rst='0')then
cntlast<="0000";
last_over<='0';
elsif(third_over'event and third_over='1')then
if( cntlast="1001")then
cntlast<="0000";
last_over<='1';
else
last_over<='0';
cntlast<= cntlast+1;
end if;
end if;
end process;

---****************显示部分***************--


process(rst,clk,div_cnt(19 downto 18))
begin
if(rst='0')then
en_xhdl<="1110";
elsif(clk'event and clk='1')then
case div_cnt(19 downto 18) is
when"00"=> en_xhdl<="1110";
when"01"=> en_xhdl<="1101";
when"10"=> en_xhdl<="1011";
when"11"=> en_xhdl<="0111";
end case;
end if;




关键词: 实验 连载 数码 logic vector sig

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