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1楼LED篇 ：

程序很简单,不用说明了吧

module ledflow(
input clk,
input rst_n,

output [7:0] leds
);

reg [7:0]leds_r;
assign leds = leds_r;

reg [24:0] clk_cnt_r;
reg en_leds_r;
reg [7:0]ledstate;
parameter leddata0 = 8'b1111_1110,
leddata1 = 8'b1111_1101,
leddata2 = 8'b1111_1011,
leddata3 = 8'b1111_0111,
leddata4 = 8'b1110_1111,
leddata5 = 8'b1101_1111,
leddata6 = 8'b1011_1111,
leddata7 = 8'b0111_1111;
/////////////17D7840 = 25M ////////////////////////////////
always @ (posedge clk or negedge rst_n)
if(!rst_n)
clk_cnt_r <= 25'd0;
else
begin
clk_cnt_r <= clk_cnt_r + 1'b1;
case(clk_cnt_r)
25'h17D7840 : begin clk_cnt_r <= 25'd0; en_leds_r <= 1'b1; end
default : en_leds_r <= 1'b0;
endcase
end

always @ (posedge clk or negedge rst_n)
if(!rst_n)
begin
leds_r <= 8'b0000_0000;
ledstate <= leddata0;
end
else
begin
if(en_leds_r)
begin
case(ledstate)
leddata0 : begin leds_r <= leddata0; ledstate <= leddata1; end
leddata1 : begin leds_r <= leddata1; ledstate <= leddata2; end
leddata2 : begin leds_r <= leddata2; ledstate <= leddata3; end
leddata3 : begin leds_r <= leddata3; ledstate <= leddata4; end
leddata4 : begin leds_r <= leddata4; ledstate <= leddata5; end
leddata5 : begin leds_r <= leddata5; ledstate <= leddata6; end
leddata6 : begin leds_r <= leddata6; ledstate <= leddata7; end
leddata7 : begin leds_r <= leddata7; ledstate <= leddata0; end
default : begin leds_r <= 8'b11111111;ledstate<=leddata0;end
endcase
end
end
endmodule

2楼按键篇,

今天晚上闲暇时间根据51FPGA的按键部分的教程写的一个简单的按键控制数码管循环显示的程序。

验证码为啥总是错误

module Key_Smg(
input clk,rst_n,
input Keyin,
output smgen,
output [7:0] KeyData
);


assign smgen = 0;

wire Key_S;
reg Key_D;
wire Key_down;

always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
Key_D <= 1'b1;
end
else
Key_D <= Keyin;

reg Key_D_t;
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
Key_D_t <= 1'b1;
end
else
Key_D_t <= Key_D;

assign Key_S = Key_D_t && (~Key_D);

reg [3:0] Smgbit;

always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
Smgbit <= 4'd0;
end
else if(Key_down)
if(Smgbit == 4'd9)
Smgbit <= 4'd0;
else
Smgbit <= Smgbit + 1'b1;
else
Smgbit <= Smgbit;

reg [15:0] delay_r;
reg [4:0] delay_cnt_r;

always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
delay_r <= 16'd0;
end
else if(Key_S)
delay_r <= 16'd0;
else if(delay_r == 16'hC350)
delay_r <= 16'd0;
else
delay_r <= delay_r + 1'b1;

always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
delay_cnt_r <= 5'd0;
end
else
if(Key_S || (delay_cnt_r == 5'd20)) delay_cnt_r <= 5'd0;
else
if(delay_r == 16'hC350)
delay_cnt_r <= delay_cnt_r + 1'b1;
else
delay_r <= delay_r;

reg Key_D2;
always @(posedge clk or negedge rst_n)
if(!rst_n)
Key_D2 <= 1'b1;
else if(delay_cnt_r == 5'd20)
Key_D2 <= Keyin;

reg Key_D2_t;
always @(posedge clk or negedge rst_n)
if(!rst_n)
Key_D2_t <= 1'b1;
else
Key_D2_t <= Key_D2;

assign Key_down = Key_D2_t && (~Key_D2);

reg [7:0] timedata_r;
assign KeyData = timedata_r;

always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
timedata_r <= 8'hff;
end
else
case(Smgbit)
4'b0000 : timedata_r <= 8'hC0; //0
4'b0001 : timedata_r <= 8'hF9; //1
4'b0010 : timedata_r <= 8'hA4; //2
4'b0011 : timedata_r <= 8'hB0; //3
4'b0100 : timedata_r <= 8'h99; //4
4'b0101 : timedata_r <= 8'h92; //5
4'b0110 : timedata_r <= 8'h82; //6
4'b0111 : timedata_r <= 8'hF8; //7
4'b1000 : timedata_r <= 8'h80; //8
4'b1001 : timedata_r <= 8'h90; //9
4'b1010 : timedata_r <= 8'hBF; //-
default : timedata_r <= 8'hff;
endcase


endmodule