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数码管60计数的程序：

module clock(clk_50m,rstc,sm_seg_out,sm_bit_out);
input clk_50m;
input rstc;
output [7:0] sm_seg_out;
output [7:0] sm_bit_out;
reg [7:0] sm_seg_out;
reg [7:0] sm_bit_out;
reg [4:0] dis_dat;
reg [2:0] dis_loca;
reg [3:0] sec11;
reg [2:0] sec12;
parameter width = 15;
reg flags,flag1ms;
reg [width:0] cntms;
reg [24:0] cnt;
wire clk_s;
parameter fre = 2499_9999;

/////////////////DivFrequen//////////////////
always @(posedge clk_50m or negedge rstc)
begin
if(!rstc)
cnt<=1'b0;
else
if(cnt == fre)
begin
cnt <= 1'b0;
flags <= ~flags;
end
else
cnt <= cnt + 1'b1;
end
assign clk_s = flags;
/*******************1ms*****************************/
always @(posedge clk_50m or negedge rstc)
begin
if(!rstc)
cntms<=16'd0;
else
begin
if(cntms == 16'd49999)
cntms <= 16'd0;
else cntms <= cntms + 1'b1;
end
end
/*******************second*****************************/
always @(posedge clk_s or negedge rstc)
begin
if(!rstc)
begin
sec11 <= 1'b0;
sec12 <= 1'b0;
end
else
begin
if((sec11 == 4'b1001)&&(sec12 ==3'b101))
begin
sec11 <= 1'b0;
sec12 <= 1'b0;
end
else
begin
if(sec11 == 4'b1001)
begin
sec11 <= 1'b0;
sec12 <= sec12 + 1'b1;
end
else
begin
sec12 <= sec12;
sec11 <= sec11 + 1'b1;
end
end
end
end
//////////////display/////////////////
always @(posedge clk_50m or negedge rstc)
begin
if(!rstc)
dis_loca <= 3'd0;
else
begin
if(cntms == 49999)
dis_loca <= dis_loca + 1'b1;
else dis_loca <= dis_loca;
end
end
always @(dis_loca)
case(dis_loca)
3'b000 : sm_bit_out = 8'b1111_1110; //第一位数码管
3'b001 : sm_bit_out = 8'b1111_1101; //第一位数码管
3'b010 : sm_bit_out = 8'b1111_1011;
3'b011 : sm_bit_out = 8'b1111_0111;
3'b100 : sm_bit_out = 8'b1110_1111;
3'b101 : sm_bit_out = 8'b1101_1111;
3'b110 : sm_bit_out = 8'b1011_1111;
3'b111 : sm_bit_out = 8'b0111_1111; //第8位
default : sm_bit_out = 8'b1111_1111;
endcase

always @(sm_bit_out or sec11 or sec12)
case(sm_bit_out)
8'b1111_1110 : dis_dat = sec11;
8'b1111_1101 : dis_dat = sec12;
8'b1111_1011 : dis_dat = 4'b1010;
8'b1111_0111 : dis_dat = sec11;
8'b1110_1111 : dis_dat = sec12;
8'b1101_1111 : dis_dat = 4'b1010;
8'b1011_1111 : dis_dat = sec11; // 问题行
8'b0111_1111 : dis_dat = sec12;
default : dis_dat = 4'b1011;
endcase
always @(dis_dat)
case(dis_dat)
4'b0000 : sm_seg_out = 8'hc0; //0
4'b0001 : sm_seg_out = 8'hf9; //1
4'b0010 : sm_seg_out = 8'ha4; //2
4'b0011 : sm_seg_out = 8'hb0; //3
4'b0100 : sm_seg_out = 8'h99; //4
4'b0101 : sm_seg_out = 8'h92; //5
4'b0110 : sm_seg_out = 8'h82; //6
4'b0111 : sm_seg_out = 8'hf8; //7
4'b1000 : sm_seg_out = 8'h80; //8
4'b1001 : sm_seg_out = 8'h90; //9
4'b1010 : sm_seg_out = 8'hbf; //-
4'b1011 : sm_seg_out = 8'hff; //消除残影
default : sm_seg_out = 8'hff; //消除残影
endcase
endmodule

为毛第7位总是不显示，图传了半天喘不上来，而《手把手教你学CPLD》中的数码动态显示管例程第7位却可以显示，代码如下：

module scan_led (sys_clk ,
sys_rstn ,
sm_seg ,
sm_bit
);
//??/????
input sys_clk ;
input sys_rstn ;
output [7:0] sm_seg ;
output [7:0] sm_bit ;
//?????
reg [7:0] sm_seg ;
reg [7:0] sm_bit ;
reg [4:0] dataout_buf ;
reg [2:0] disp_dat ;
reg [15:0] delay_cnt ;
//????
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
delay_cnt<=16'd0;
else
begin
if(delay_cnt==16'd49999)
delay_cnt<=16'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
if(!sys_rstn)
disp_dat<=4'd0;
else
begin
if(delay_cnt==16'd49999)
disp_dat<=disp_dat+1'b1;
else
disp_dat<=disp_dat;
end
end
always @(disp_dat)
begin
case(disp_dat)
3'b000 :
sm_bit = 8'b1111_1110;
3'b001 :
sm_bit = 8'b1111_1101;
3'b010 :
sm_bit = 8'b1111_1011;
3'b011 :
sm_bit = 8'b1111_0111;
3'b100 :
sm_bit = 8'b1110_1111;
3'b101 :
sm_bit = 8'b1101_1111;
3'b110 :
sm_bit = 8'b1011_1111;
3'b111 :
sm_bit = 8'b0111_1111;
default :
sm_bit = 8'b1111_1110;
endcase
end

always@(sm_bit)
begin
case(sm_bit)
8'b1111_1110:
dataout_buf=0;
8'b1111_1101:
dataout_buf=1;
8'b1111_1011:
dataout_buf=2;
8'b1111_0111:
dataout_buf=3;
8'b1110_1111:
dataout_buf=4;
8'b1101_1111:
dataout_buf=5;
8'b1011_1111:
dataout_buf=6;
8'b0111_1111:
dataout_buf=7;
default:
dataout_buf=8;
endcase
end

always@(dataout_buf)
begin
case(dataout_buf)
4'h0 : sm_seg = 8'hc0; // "0"
4'h1 : sm_seg = 8'hf9; // "1"
4'h2 : sm_seg = 8'ha4; // "2"
4'h3 : sm_seg = 8'hb0; // "3"
4'h4 : sm_seg = 8'h99; // "4"
4'h5 : sm_seg = 8'h92; // "5"
4'h6 : sm_seg = 8'h82; // "6"
4'h7 : sm_seg = 8'hf8; // "7"
4'h8 : sm_seg = 8'h80; // "8"
4'h9 : sm_seg = 8'h90; // "9"
4'ha : sm_seg = 8'h88; // "a"
4'hb : sm_seg = 8'h83; // "b"
4'hc : sm_seg = 8'hc6; // "c"
4'hd : sm_seg = 8'ha1; // "d"
4'he : sm_seg = 8'h86; // "e"
4'hf : sm_seg = 8'h8e; // "f"
default :
sm_seg = 8'hc0; // "0"
endcase
end
endmodule

这是为嘛？感觉两个差不多啊，求指教