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htbadboy-进程贴,数字钟(可调时)

菜鸟
2013-08-09 22:04:13 打赏

数字钟:有按键消抖,s1键调小时,s2键调分钟,s3键对s清零,另外附带呼吸灯,到59m时开始呼吸,也可以改成倒数8s,led倒计时。

module clock(clk_50m,rstc,keys,sm_seg_out,sm_bit_out,ledbre);
input clk_50m; //50M jing zhen
input rstc; //fu wei
input [2:0] keys; //s qing 0:keys[2]; tiao fen :keys[1];tiao shi :keys[0]
//reg [3:0] ledcnt; //8s led dao ji shi
/*****************???**********************/
output [7:0] ledbre; //led shu chu
reg [7:0] ledbre;
reg [27:0] counter; //hu xi deng zhou qi tiao zheng
reg [6:0] PWM_adj;
reg [7:0] PWM_width;
/*******************??***********************/
reg [19:0] cnt20ms; //ji shi 20ms: jian pan xiao dou
reg [2:0] key_samp1; //20ms qian jian pan cai yang
reg [2:0] key_samp2; //20ms hou jian pan cai yang
reg [2:0] key_samp1_lock; //20ms qian cai yang ji cun
reg [2:0] key_samp2_lock ; //20ms hou cai yang ji cun
wire [2:0] key_change1; //pan duan shi fou you an jian an xia
wire [2:0] key_change2; //20ms hou shi fou an jian zhi bian dong
reg [2:0] okeys; //an jian shu chu
/*************display***************/
output [7:0] sm_seg_out; //shu ma guan duan xuan
output [7:0] sm_bit_out; //wei xuan
reg [7:0] sm_seg_out;
reg [7:0] sm_bit_out;
reg [4:0] dis_dat; //shu chu shu zi
reg [2:0] dis_loca; //shu ma guan cao miao
reg [3:0] sec11,min11; //s ge wei ,m ge wei
reg [2:0] sec12,min12; //s shi wei,m shi wei
reg [3:0] hou11;
reg [1:0] hou12;
parameter width = 15; //1ms ji shi
reg [width:0] cntms; //1ms ji shi
reg [26:0] cnt; //1s ji shi
parameter fre = 4999_9999; // 1s
/******************jian pan xiao dou kai shi**************************/
always @(posedge clk_50m or negedge rstc)
if(!rstc)
key_samp1 <= 3'b111;
else
key_samp1 <= keys; //dui keys cai yang

always @(posedge clk_50m or negedge rstc)
if(!rstc)
key_samp1_lock <= 3'b111;
else
key_samp1_lock <= key_samp1; //dui keys cai yang zhi ji cun
assign key_change1 = key_samp1_lock & (~key_samp1); //key_change1 pan duan shi fou you an jian an xia
///////////////////////////////////////////////////////
always @(posedge clk_50m or negedge rstc)
if(!rstc)
cnt20ms <= 20'b0;
else if(key_change1) //you an jian an xia ji dui 20ms ji shu qi qing 0
cnt20ms <= 20'b0;
else
cnt20ms <= cnt20ms + 1'b1;
always @(posedge clk_50m or negedge rstc) //20ms yan shi hou zai ci cai yang ,yi xia zhu shi tong shi
if(!rstc)
key_samp2 <= 3'b111;
else if(cnt20ms == 20'd100_0000)
begin
key_samp2 <= keys;
end
always @(posedge clk_50m or negedge rstc)
if(!rstc)
key_samp2_lock <= 3'b111;
else
key_samp2_lock <= key_samp2;
assign key_change2 = key_samp2_lock & (~key_samp2);// key_change2 = 1 biao shi que shi you an jian an xia
///////////////////////////////////////////////
always @(posedge clk_50m or negedge rstc)
if(!rstc)
okeys <= 3'b111;
else
okeys <= ~key_change2; //fu zhi gei okeys
/*************************jian pan xiao dou jie shu*******************************/
/********************* 1s fen pin*********************/
always @(posedge clk_50m or negedge rstc)
begin
if(!rstc)
cnt<=1'b0;
else if(cnt == fre)
cnt <= 1'b0;
else
cnt <= cnt + 1'b1;
end
/******************* 1ms fen pin ,yong yu shu ma guan sao miao*****************************/
always @(posedge clk_50m or negedge rstc)
begin
if(!rstc)
cntms<=16'd0;
else
begin
if(cntms == 16'd49999)
cntms <= 16'd0;
else cntms <= cntms + 1'b1;
end
end
/*******************tiao zheng shi zhong*****************************/
always @(posedge clk_50m or negedge rstc)
begin
if(!rstc)
begin
sec11 <= 1'b0;
sec12 <= 1'b0;
min11 <= 1'b0;
min12 <= 1'b0;
hou11 <= 1'b0;
hou12 <= 1'b0;
end
else if(!okeys[2]) //qing 0
begin
sec11 <= 1'b0;
sec12 <= 1'b0;
end
else if(!okeys[1]) //tiao fen
begin
min11 <= min11 + 1'b1;
if((min11 == 4'b1001)&&(min12 ==3'b101))
begin
min11 <= 1'b0;
min12 <= 1'b0;
end
else if(min11 == 4'b1001)
begin
min11 <= 1'b0;
min12 <= min12 + 1'b1;
end
end
else if(!okeys[0]) //tiao shi
begin
hou11 <= hou11 +1'b1;
if((hou11 == 4'b0011)&&(hou12 == 2'b10))
begin
hou11 <= 1'b0;
hou12 <= 1'b0;
end
else if(hou11 == 4'b1001)
begin
hou11 <= 1'b0;
hou12 <= hou12 + 1'b1;
end
end
///////////////////zheng chang ji shi/////////////////////
else if(cnt == fre)
begin
if(sec11 == 4'd9) /****************??sec11????????******************/
begin
sec11 <= 1'b0;
if(sec12 ==3'd5) /**************??sec12????????*****************/
begin
sec12 <= 1'b0;
if(min11 == 4'd9) /****************??min11*************************/
begin
min11 <= 1'b0;
if(min12 == 3'd5) /**********??min12**************/
begin
min12 <= 1'b0;
if(hou11 == 4'd9) /****??hou11*****/
begin
hou11 <= 1'b0;
hou12 <= hou12 + 1'b1;
end
//////
else
begin
if((hou12 == 2'd2)&&(hou11 == 4'd3))
begin
hou11 <= 1'b0;
hou12 <= 1'b0;
end
else
begin
hou11 <= hou11 + 1'b1;
hou12 <= hou12;
end /*hhhhhhhhhhhhhhhhhhhhhh*/
end
end
else min12 <= min12 +1'b1 ; /**********min12**************/
end
else min11 <= min11+1'b1; /*mmmmmmmmmm11mmmmmmmmm*/
end
else sec12 <= sec12+1'b1 ; /**************sec12*****************/
end
else sec11 <= sec11+1'b1; /****************sec11******************/
end
else //wei dao 1s ji xu bao chi
begin
sec11 <= sec11;
sec12 <= sec12;
min11 <= min11;
min12 <= min12;
hou11 <= hou11;
hou12 <= hou12;
end
end
////////////////////////////////////////////////////
//////////////display/////////////////
always @(posedge clk_50m or negedge rstc) //1ms
begin
if(!rstc)
dis_loca <= 3'd0;
else
begin
if(cntms == 49999)
if(dis_loca == 3'b111)
dis_loca <= 3'b000;
else
dis_loca <= dis_loca + 1'b1;
else dis_loca <= dis_loca;
end
end

always @(dis_loca)
case(dis_loca)
3'b000 : sm_bit_out = 8'b1111_1110;
3'b001 : sm_bit_out = 8'b1111_1101;
3'b010 : sm_bit_out = 8'b1111_1011;
3'b011 : sm_bit_out = 8'b1111_0111;
3'b100 : sm_bit_out = 8'b1110_1111;
3'b101 : sm_bit_out = 8'b1101_1111;
3'b110 : sm_bit_out = 8'b1011_1111;
3'b111 : sm_bit_out = 8'b0111_1111;
default : sm_bit_out = 8'b1111_1111;
endcase

always @(sm_bit_out or sec11 or sec12 or min11 or min12 or hou11 or hou12)
case(sm_bit_out)
8'b1111_1110 : dis_dat = sec11; //s ge wei
8'b1111_1101 : dis_dat = sec12;
8'b1111_1011 : dis_dat = 4'b1010;
8'b1111_0111 : dis_dat = min11; //m ge wei
8'b1110_1111 : dis_dat = min12;
8'b1101_1111 : dis_dat = 4'b1010;
8'b1011_1111 : dis_dat = hou11; //h ge wei
8'b0111_1111 : dis_dat = hou12;
default : dis_dat = 4'b1011;
endcase

always @(dis_dat)
case(dis_dat)
4'b0000 : sm_seg_out = 8'hc0; //0
4'b0001 : sm_seg_out = 8'hf9; //1
4'b0010 : sm_seg_out = 8'ha4; //2
4'b0011 : sm_seg_out = 8'hb0; //3
4'b0100 : sm_seg_out = 8'h99; //4
4'b0101 : sm_seg_out = 8'h92; //5
4'b0110 : sm_seg_out = 8'h82; //6
4'b0111 : sm_seg_out = 8'hf8; //7
4'b1000 : sm_seg_out = 8'h80; //8
4'b1001 : sm_seg_out = 8'h90; //9
4'b1010 : sm_seg_out = 8'hbf; //-
4'b1011 : sm_seg_out = 8'hff; //null shu ma guan quan mie ,ju shi yan zhe neng xiao chu
shu ma guan xian shi de can ying
default : sm_seg_out = 8'hff; //null shu ma guan quan mie ,ju shi yan zhe neng xiao chu shu ma guan xian shi de can ying
endcase
always @(posedge clk_50m or negedge rstc) //hu xi deng 1m dao ji shi huo zhe shi 8s dao ji shi
begin
if(!rstc)
begin
// counter <= 0; //8s led dao ji shi
ledbre <= 8'b1111_1111;
end
else
/*begin
if((cnt == fre)&&(min11 == 4'd9)&&(min12 == 3'd5)&&((sec11 <= 4'd9)&&(sec12 == 3'd5)&&(sec11 >= 4'd1)))
begin
if(ledcnt == 4'b1000)
ledcnt <= 4'b0;
else
ledcnt <= ledcnt + 1'b1;
end
else
case(ledcnt)
4'b0000 : ledbre <= 8'b1111_1111;
4'b0001 : ledbre <= 8'b0000_0000;
4'b0010 : ledbre <= 8'b0000_0001;
4'b0011 : ledbre <= 8'b0000_0011;
4'b0100 : ledbre <= 8'b0000_0111;
4'b0101 : ledbre <= 8'b0000_1111;
4'b0110 : ledbre <= 8'b0001_1111;
4'b0111 : ledbre <= 8'b0011_1111;
4'b1000 : ledbre <= 8'b0111_1111;
default : ledbre <= 8'b1111_1111;
endcase
end*/
begin
counter <= counter + 1'b1;
PWM_width <= PWM_width[6:0]+ PWM_adj;
if(counter[27])
PWM_adj <= counter[26:20]; //128 zhong liang du,mei zhong chi xu shi jian 2 de 20 ci fang ge ji shu
else
PWM_adj <= ~ counter[26:20];
if((min11 == 4'd9)&&(min12 == 3'd5))
begin
ledbre[0] <= PWM_width[7];
ledbre[1] <= PWM_width[7];
ledbre[2] <= PWM_width[7];
ledbre[3] <= PWM_width[7];
ledbre[4] <= PWM_width[7];
ledbre[5] <= PWM_width[7];
ledbre[6] <= PWM_width[7];
ledbre[7] <= PWM_width[7];
end
else ledbre <= 8'b1111_1111;
end
end

endmodule

有个很严重的问题:

这款入门级CPLD芯片居然只有240个逻辑资源,严重不足啊。在公司电脑(32位Xp)上编译(好像是quartus ii 6.0还是什么),共占用235个,回来用自己的电脑(win7 64位)quartus ii v10.0上编译,占用245个,逻辑资源不够了,什么情况?

本来来有中文注释的,,但是上面中文乱码了,变成?了,改成拼音了,我把源文件传上来。clock_h.zip

乱码貌似是quartus版本问题,用公司电脑打开是正常显示的,在quartusii 10.0里变成?了。上网查了下,说从

7.0之后就不支持中文了,




关键词: CPLD FPGA verilog 数字钟

菜鸟
2013-08-10 23:08:28 打赏
2楼

把你呼吸灯部分去掉,就可以了

我移植到我的板子上,去掉呼吸灯就可以了


菜鸟
2013-08-11 09:11:33 打赏
3楼
那为毛32位XP就可以呢

菜鸟
2013-08-11 11:52:15 打赏
4楼
不知道哦,不去呼吸灯的时候,说需要248个逻辑模块,编译报错

高工
2013-08-11 18:07:03 打赏
5楼
当年的cpld!实验就是这个,不过是逻辑器件画

高工
2013-08-11 19:07:21 打赏
6楼
吼吼,用逻辑图的形式做这个,赶脚很麻烦。

高工
2013-08-21 10:07:09 打赏
7楼
不错,加油继续!

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