EEPW论坛

楼主能否说的再详细些？

作业最好在帖子里面显示，不上上传附件

嘻嘻！

受教了

//间隔点亮发光二极管

module led_interval

(sys_rst,
sys_clk,
led);

input sys_rst;
input sys_clk;
output led;

reg [3:0] led;
reg [25:0] delay_cnt;
reg [2:0] display;

always@(posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
delay_cnt<=26'd0;
else if(delay_cnt==26'd49999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end


always@(posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
display<=2'd0;
else if(delay_cnt==26'd49999999)
display<=display+1'b1;
else
display<=display;
end

always@(display)
begin
case(display)
3'h1: led=4'b1110;
3'h2: led=4'b1111;
3'h3: led=4'b1011;
3'h4: led=4'b1111;
3'h5: led=4'b1101;
3'h6: led=4'b1111;
3'h7: led=4'b0111;
3'h8: led=4'b1111;
endcase
end
endmodule

//向左流水灯功能

module led_yjg (sys_rst,
sys_clk,
led);
input sys_rst;
input sys_clk;
output led;
reg [3:0] led;
reg [25:0] delay_cnt;
reg [1:0] display;
always @ (posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
delay_cnt<=26'd0;
else if(delay_cnt==26'd49999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
always @ (posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
display<=2'd0;
else if(delay_cnt==26'd49999999)
display<=display+1'b1;
else
display<=display;
end
always @ (display)
begin
case(display)
2'h1: led=4'b0111;
2'h2: led=4'b0011;
2'h3: led=4'b0001;
2'h4: led=4'b0000;
endcase
end
endmodule

//向右跑马灯功能

module horse_lamp_right (sys_rst,
sys_clk,
led);
input sys_rst;
input sys_clk;
output led;
reg [3:0] led;
reg [25:0] delay_cnt;
reg [1:0] display;
always @ (posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
delay_cnt<=26'd0;
else if(delay_cnt==26'd49999999)
delay_cnt<=26'd0;
else
delay_cnt<=delay_cnt+1'b1;
end
always @ (posedge sys_clk or negedge sys_rst)
begin
if(!sys_rst)
display<=2'd0;
else if(delay_cnt==26'd49999999)
display<=display+1'b1;
else
display<=display;
end
always @ (display)
begin
case(display)
2'h1: led=4'b1110;
2'h2: led=4'b1101;
2'h3: led=4'b1011;
2'h4: led=4'b0111;
endcase
end
endmodule

敬请各位老师同行批评指正，程序哪些地方需要更改简化等等。。。。，真心期待