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3-5用VHDLSHEJIYIGE3-8译码器，要求分别用赋值语句,case语句,if-else语句或移位操作符来完成。比较这4种方式中，那一种更节省逻辑资源。

本题用的是74LS138真值表：

一 顺序赋值语句1 CASE语句,2 IF-ELSE语句

1.case语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decoder3to8 IS

PORT(A0,A1, A2 ,S0,S1,S2 : IN STD_LOGIC;

Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

）;

END ENTITY decoder3to8;

ARCHITECTURE BEH38 OF decoder3to8 IS

SIGNAL DATA: STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGIN

DATA<= A0&A1&A2;

PROCESS(DATA,S0,S1,S2,)

BEGIN

IF S0='1' and S1='0' and S2='0') THEN

CASE(DATA) IS

WHEN "000" => y <="11111110";

WHEN "001" => y <="11111101";

WHEN "010" => y <="11111011";

WHEN "011" => y <="11110111";

WHEN "100" => y <="11101111";

WHEN "101" => y <="11011111";

WHEN "110" => y <="10111111";

WHEN "111" => y <="01111111";

WHEN OTHERS => y <="11111111";

END CASE;

END IF;

END PROCESS;

END ARCHITECTURE BEH38;

2.If-else语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decoder3to8 IS

PORT(A0,A1, A2 ,S0,S1,S2 : IN STD_LOGIC;

Y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

）;

END ENTITY decoder3to8;

ARCHITECTURE BEH38 OF decoder3to8 IS

SIGNAL DATA: STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGIN

DATA<= A0&A1&A2;

PROCESS(DATA,S0,S1,S2,)

BEGIN

IF (S0='1' and S1='0' and S2='0') THEN

IF (DATA= "000") THEN y<="11111110";

ELSIF (DATA= "001") THEN y<="11111101";

ELSIF (DATA= "010") THEN y<="11111011";

ELSIF (DATA= "011" )THEN y<="11110111";

ELSIF (DATA= "100" )THEN y<="11101111";

ELSIF (DATA= "101" ) THEN y<="11011111";

ELSIF (DATA= "110" ) THEN y<="10111111";

ELSIF (DATA= "111" ) THEN y<="01111111";

ELSE y<="11111111";

END IF;

END PROCESS;

END ARCHITECTURE BEH38;

二：并行赋值语句1WHEN-ELSE语句2.WITH-SELECT语句

1．WHEN-ELSE语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decoder3to8 IS

PORT(A0,A1, A2 ,S0,S1,S2 : IN STD_LOGIC;

Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

）;

END ENTITY decoder3to8;

ARCHITECTURE BEH38 OF decoder3to8 IS

SIGNAL DATA: STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGIN

DATA<= A0&A1&A2;

IF （S0='1' and S1='0' and S2='0') THEN

y <="11111110" WHEN DATA ="000" ELSE

"11111101" WHEN DATA="001" ELSE

"11111011" WHEN DATA="010" ELSE

"11110111" WHEN DATA="011" ELSE

"11101111" WHEN DATA="100" ELSE

"11011111" WHEN DATA="101" ELSE

"10111111" WHEN DATA="110" ELSE

"01111111" WHEN DATA="111" ELSE

y <="11111111" ;

END IF

END ARCHITECTURE BEH38;

2.WITH-SELECT语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY decoder3to8 IS

PORT(A0,A1, A2 ,S0,S1,S2 : IN STD_LOGIC;

Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)

）;

END ENTITY decoder3to8;

ARCHITECTURE BEH38 OF decoder3to8 IS

SIGNAL DATA: STD_LOGIC_VECTOR (2 DOWNTO 0);

BEGIN

DATA<= A0&A1&A2;

WITH DATA SELECT

IF （S0='1' and S1='0' and S2='0') THEN

y <="11111110"; WHEN "000"

"11111101" WHEN "001"

"11111011" WHEN "010"

"11110111" WHEN "011"

"11101111" WHEN "100"

"11011111" WHEN "101"

"10111111" WHEN "110"

"01111111" WHEN "111"

ELSE

y <= "11111111" ;

END IF

END ARCHITECTURE BEH38;

三.移位操作符

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENEITY decoder3to8 IS

PORT (DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0);

DOUT:OUT BIT_ VECTOR( 7 DOWNTO 0)

);

END decoder3to8 ;

ARCHITECTURE BEH38 OF decoder3to8 IS

BEGIN

DOUT<=“11111110”SLL CONV_ INTEGER(DIN);

END ARCHITECTURE BEH38 ;

所以四种综合看移位操作符比较节省逻辑资源。

3-14用循环语句设计一个7人投票表决器。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENEITY CNTC IS;

PORT (DIN : IN STD_LOGIC_VECTOR (6 DOWNTO 0);

DOUT: OUT BIT_ VECTOR( 2 DOWNTO 0)

Y:OUT STD_LOGIC;

);

END ENEITY CNTC;

ARCHITECTURE ONE OF CNTC IS

BEGIN

PROCESS (DIN)

VARIABLE Q : STD_LOGIC_VECTO(2 DOWNTO 0);

BEGIN

Q :=”000”;

FOR n in 0 to 6 LOOP

IF (DIN(n)=’1’) THEN Q:=Q+1;

END IF;

END LOOP;

CNTC<=Q;

IF（CNTC >=‘100’）THEN Y=’1’

ELSE Y=’0’;

END PROCESS;

END ARCHITECTURE ONE；