EEPW论坛

时钟通过PLL倍频，是满足要求的。

/****************************************************************************** *Engineer: superdian *Create Date: 2014/9/29 *Design Name: *Module Name: VGA *Project Name: *Target Devices: EP3CE5E144C8 *Tool versions: *Description: * *Dependencies: * *Revision: *Revision 0.01 - File Created *Additional Comments: ******************************************************************************/ module VGA(clock,switch,disp_RGB,hsync,vsync); input clock;//系统输入时钟80MHZ input [1:0] switch; output [2:0] disp_RGB;//VGA数据输出 output hsync; //vga行同步信号 output vsync; //vga场同步信号 reg [10:0] hcount;//vga行扫描计数器 reg [10:0] vcount;//vga场扫描计数器 reg [2:0] data; reg [2:0] h_dat; reg [2:0] v_dat; reg flag; wire hcount_ov; wire vcount_ov; wire dat_act; wire hsync; wire vsync; reg vga_clk; //vga行场扫描时序参数表 parameter hsync_end = 11'd127, hdat_begin = 11'd215, hdat_end = 11'd1015, hpixel_end = 11'd1055, vsync_end = 11'd3, vdat_begin = 11'd26, vdat_end = 11'd626, vline_end = 11'd627; always @(posedge clock) begin vga_clk = ~vga_clk; end /**************************** VGA驱动部分 ****************************/ //行扫描 always@ (posedge vga_clk) begin if(hcount_ov) hcount <= 11'd0; else hcount <= hcount + 1'd1; end assign hcount_ov = (hcount == hpixel_end); //场扫描 always@(posedge vga_clk) begin if(hcount_ov) begin if(vcount_ov) vcount <= 11'd0; else vcount <= vcount + 1'd1; end end assign vcount_ov = (vcount == vline_end); //数据,信号同步传输 assign dat_act = ((hcount >= hdat_begin)&&(vcount = vdat_begin) && (vcount < vdat_end)); assign hsync = (hcount > hsync_end); assign vsync = (vcount > vsync_end); assign disp_RGB = (dat_act) ? data:3'h00; always @(posedge vga_clk) begin case(switch[1:0]) 2'd0: data <= h_dat; //横彩条 2'd1: data <= v_dat; //选择竖彩条 2'd2: data <= (v_dat ^ h_dat); //异或产生棋盘格 2'd3: data <= (v_dat ~^ h_dat); //同或产生棋盘格 endcase end always @(posedge vga_clk)//产生竖彩条 begin if(hcount <315) v_dat <= 3'h7; //白 else if(hcount < 415) v_dat <= 3'h6; //黄 else if(hcount < 515) v_dat <= 3'h5; //青 else if(hcount < 615) v_dat <= 3'h4; //绿 else if(hcount < 715) v_dat <= 3'h3; //紫 else if(hcount < 815) v_dat <= 3'h2;//红 else if(hcount < 915) v_dat <= 3'h1; //蓝 else v_dat <= 3'h0; //黑 end always@(posedge vga_clk)//产生横彩条 begin if(vcount <101) h_dat <= 3'h7; //白 else if(vcount < 176) h_dat <= 3'h6; //黄 else if(vcount < 251) h_dat <= 3'h5; //青 else if(vcount < 326) h_dat <= 3'h4; //绿 else if(vcount < 401) h_dat <= 3'h3; //紫 else if(vcount < 476) h_dat <= 3'h2; //红 else if(vcount < 551) h_dat <= 3'h1; //蓝 else h_dat <= 3'h0; //黑 end endmodule

这是我修改后的参数。