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习题3-3

（1）IF_THEN语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

PORT (A,B,C,D,S0,S1,S2,S3 : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

BEGIN

PROCESS(S0,S1,S2,S3,A,B,C,D)

BEGIN

IF S0=’0’ AND NOT(S1=’0’ OR S2=’0’ OR S3=’0’) THEN Y<=A;

ELSIF S1=’0’ AND NOT(S0=’0’ OR S2=’0’ OR S3=’0’) THEN Y<=B;

ELSIF S2=’0’ AND NOT(S0=’0’ OR S1=’0’ OR S3=’0’) THEN Y<=C;

ELSIF S3=’0’ AND NOT(S0=’0’ OR S1=’0’ OR S2=’0’) THEN Y<=D;

END NULL;

END IF;

END PROCESS;

END BHV;

(2)WHEN_ELSE语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

PORT (A,B,C,D,S0,S1,S2,S3 : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

BEGIN

PROCESS(S0,S1,S2,S3,A,B,C,D)

BEGIN

Y<=A WHEN S0=’0’ AND NOT(S1=’0’ OR S2=’0’ OR S3=’0’) ELSE

B WHEN S1=’0’ AND NOT(S0=’0’ OR S2=’0’ OR S3=’0’) ELSE

C WHEN S2=’0’ AND NOT(S0=’0’ OR S1=’0’ OR S3=’0’) ELSE

D WHEN S3=’0’ AND NOT(S0=’0’ OR S1=’0’ OR S2=’0’) ELSE

NULL ;

END PROCESS;

END BHV;

(3)CASE语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

PORT (A,B,C,D,S0,S1,S2,S3 : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

SIGNAL S : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

S <= S3 & S2 & S1 & S0;

PROCESS(S3,S2,S1,S0)

BEGIN

CASE (S) IS

WHEN “1110” => Y<=A;

WHEN “1101” => Y<=B;

WHEN “1011” => Y<=C;

WHEN “0111” => Y<=D;

WHEN OTHERS => NULL;

END CASE;

END PROCESS;

END BHV;

(4)WITH_SELECT语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

PORT (A,B,C,D,S0,S1,S2,S3 : IN STD_LOGIC;

Y : OUT STD_LOGIC);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

SIGNAL S : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

S <= S3 & S2 & S1 & S0;

PROCESS(S3,S2,S1,S0)

BEGIN

WITH S SELECT

Y<=A WHEN “1110”,

B WHEN “1101”,

C WHEN “1011”,

D WHEN “0111” ;

END PROCESS;

END BHV;

习题3-4

（1）半减器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY h_suber IS

PORT ( x, y : IN STD_LOGIC;

diff, s_out : OUT STD_LOGIC);

END ENTITY h_suber;

ARCHITECTURE fh1 OF h_suber IS

BEGIN

s_out <= (NOT x ) AND y;

diff <= x XOR y;

END ARCHITECTURE fh1;

(2)全减器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY f_suber IS

PORT ( X,Y,sub_in : IN STD_LOGIC;

diff,s_out : OUT STD_LOGIC);

END ENTITY f_suber;

ARCHITECTURE fd1 OF f_suber IS

COMPONENT h_suber

PORT (x ,y : IN STD_LOGIC; s_out ,diff : OUT STD_LOGIC);

END COMPONENT;

SIGNAL net1, net2, net3: STD_LOGIC;

BEGIN

u1 : h_suber PORT MAP(x=>X, y=>Y, diff=>net1, s_out=>net2);

u2 : h_suber PORT MAP(x=>net1, y=>sub_in, diff=>diffr, s_out=>net3);

sub_out <= net2 OR net3;

END fd1;