蜂鸣器报警

蜂鸣器报警
/*--------------------------------------------------------
-- Engineer: zhrscut
-- Create Date:
-- Module Name:
-- Tool Versions: Quartus_II 9.1
-- 欢迎加入 EEPW ，FPGA 开发板 DIY 活动
--------------------------------------------------------*/
module beep(clk,beep);
input clk;
output beep;
reg[21:0] cnt;


always @(posedge clk )
if(cnt<22'd3_000000) cnt<=cnt+1'b1;
else cnt<=0;

assign beep=(cnt<=22'd1500000)? 1'b1:1'b0;

endmodule