如何使用STATECAD进行多状态机设计实例分析

　　Dcounter0,Dcounter1 : OUT Std_logic);

　　SIGNAL BP_dcounter0,BP_dcounter1,Readcounter0,Readcounter1: Std_logic;

　　END;

　　ARCHITECTURE BEHAVIOR OF SHELL_DUOZTJI IS

　　SIGNAL Sreg : Std_logic_vector (1 DOWNTO 0);

　　SIGNAL Next_sreg : Std_logic_vector (1 DOWNTO 0);

　　CONSTANT M0full : Std_logic_vector (1 DOWNTO 0) :="00";

　　CONSTANT M0writewait : Std_logic_vector (1 DOWNTO 0) :="01";

　　CONSTANT STATE0 : Std_logic_vector (1 DOWNTO 0) :="10";

　　CONSTANT Write0 : Std_logic_vector (1 DOWNTO 0) :="11";

　　SIGNAL Sreg1 : Std_logic_vector (1 DOWNTO 0);

　　SIGNAL Next_sreg1 : Std_logic_vector (1 DOWNTO 0);

　　CONSTANT M0empty : Std_logic_vector (1 DOWNTO 0) :="00";

　　CONSTANT M0readwait : Std_logic_vector (1 DOWNTO 0) :="01";

　　CONSTANT Read0 : Std_logic_vector (1 DOWNTO 0) :="10";

　　CONSTANT STATE1 : Std_logic_vector (1 DOWNTO 0) :="11";

　　SIGNAL Next_BP_dcounter0,Next_BP_dcounter1,Next_readcounter0,

　　Next_readcounter1 : Std_logic;

　　SIGNAL BP_dcounter : Std_logic_vector (1 DOWNTO 0);

　　SIGNAL Dcounter : Std_logic_vector (1 DOWNTO 0);

　　SIGNAL Readcounter : Std_logic_vector (1 DOWNTO 0);