如何使用STATECAD进行多状态机设计实例分析

　　ELSE

　　Next_sreg1=M0readwait;

　　Readcounter = (( Std_logic_vector''(Readcounter1, Readcounter0)));

　　END IF;

　　WHEN Read0 =>

　　IF ( Readcounter0=''1'' AND Readcounter1=''1'' ) THEN

　　Next_sreg1=M0empty;

　　Readcounter = (Std_logic_vector''("00"));

　　ELSE

　　Next_sreg1=Read0;

　　Readcounter = (( Std_logic_vector''(Readcounter1, Readcounter0)) +

　　Std_logic_vector''("01"));

　　END IF;

　　WHEN STATE1 =>

　　IF ( (Sreg=M0full)) THEN

　　Next_sreg1=Read0;

　　Readcounter = (( Std_logic_vector''(Readcounter1, Readcounter0)) + Std_logic_vector''("01"));

　　ELSE

　　Next_sreg1=STATE1;

　　Readcounter = (( Std_logic_vector''(Readcounter1, Readcounter0)));

　　END IF;

　　WHEN OTHERS =>

　　END CASE;