器件名称:
CD54ACT273
功能描述:
Octal D Flip-Flop with Reset
文件大小:
36.93KB 共8页
简 介:
Data sheet acquired from Harris Semiconductor SCHS249A CD54AC273, CD74AC273 CD54ACT273, CD74ACT273 Octal D Flip-Flop with Reset Description The ’AC273 and ’ACT273 devices are octal D-type ip-ops with reset that utilize advanced CMOS logic technology. Information at the D input is transferred to the Q output on the positive-going edge of the clock pulse. All eight ip-ops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. August 1998 - Revised April 2000 Features Buffered Inputs Typical Propagation Delay - 6.5ns at VCC = 5V, TA = 25oC, CL = 50pF Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 SCR-Latchup-Resistant CMOS Process and Circuit Design Speed of Bipolar FAST/AS/S with Signicantly Reduced Power Consumption Balanced Propagation Delays AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply ±24mA Output Drive Current - Fanout to 15 FAST ICs - Drives 50 Transmission Lines Ordering Information PART NUMBER CD74AC273E CD54AC273F3A CD74ACT273E CD54ACT273F3A CD74AC273M CD74ACT273M TEMPERATURE RANGE -40oC to 85oC -55oC to 125oC -40oC to 85oC -55oC to 125oC -40oC to 85oC -40oC to 85oC PACKAGE 20 Ld PDIP 20 Ld CDIP 20 Ld PDIP 20 Ld CDIP 20 Ld SOIC 20 Ld SOIC Pinout CD54AC273, CD54ACT273 (CDIP) CD74AC273, CD74ACT273 (PDIP, SOIC) TOP VIEW MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP NOTE……
