器件名称:
CD54ACT273
功能描述:
Octal D Flip-Flop with Reset
文件大小:
10.34KB 共1页
简 介:
S E M I C O N D U C T O R CD54AC273/3A CD54ACT273/3A Octal D Flip-Flop with Reset Functional Diagram CLOCK CP D0 D1 D2 DATA INPUTS D3 D4 D5 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 DATA OUTPUTS June 1997 COMPLETE DATA SHEET COMING SOON! Description The CD54AC273/3A and CD54ACT273/3A are octal D ipops with reset that utilize the Harris Advanced CMOS Logic technology. Information at the D input is transferred to the Q output on the positive-going edge of the clock pulse. All eight ip-ops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low-voltage level independent of the clock. The CD54AC273/3A and CD54ACT273/3A are supplied in 20 lead dual-in-line ceramic packages (F sufx). ACT INPUT LOAD TABLE D6 INPUT Dn MR CP NOTE: UNIT LOAD (NOTE 1) D7 0.5 0.57 RESET MR 1 1. Unit load is ICC limit specied in DC Electrical Specications Table, e.g., 2.4mA Max at +25oC. Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current, Per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or GND Current, ICC or IGND For Up to 4 Outputs Per Device, Add ±25mA For Each Additional Output . . . . . . . . . . . . . ……
