器件名称:
MC74AC377
功能描述:
OCTAL D FLIP-FLOP WITH CLOCK ENABLE
文件大小:
199.51KB 共6页
简 介:
MC74AC377 MC74ACT377 Octal D FlipFlop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Ideal for Addressable Register Applications Clock Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock Outputs Source/Sink 24 mA See MC74AC273 for Master Reset Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version ′ACT377 Has TTL Compatible Inputs VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 DW SUFFIX CASE 751D-04 PLASTIC OCTAL D FLIP-FLOP WITH CLOCK ENABLE N SUFFIX CASE 738-03 PLASTIC LOGIC SYMBOL 1 CE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND CP CE O0 O1 O2 O3 O4 O5 O6 O7 D0 D1 D2 D3 D4 D5 D6 D7 PIN NAMES D0–D7 CE Q0–Q7 CP Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input MODE SELECT-FUNCTION TABLE Inputs Operating Mode CP Load ′1′ Load ′0′ Hold (Do Nothing) X CE L L H H Dn H L X X Qn H L No Change No Change Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immateria……
