器件名称:
MC74AC377
功能描述:
Octal D FlipFlop with Clock Enable
文件大小:
122.9KB 共10页
简 介:
MC74AC377, MC74ACT377 Octal D FlipFlop with Clock Enable The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features http://onsemi.com PDIP20 N SUFFIX CASE 738 1 Ideal for Addressable Register Applications Clock Enable for Address and Data Synchronization Applications Eight Edge-Triggered D Flip-Flops Buffered Common Clock Outputs Source/Sink 24 mA See MC74AC273 for Master Reset Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version ACT377 Has TTL Compatible Inputs MSL = 1 for all Surface Mount Chip Complexity: 292 FETs or 73 Gates PbFree Packages are Available SOIC20W DW SUFFIX CASE 751D 1 TSSOP20 DT SUFFIX CASE 948E 1 VCC 20 O7 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11 1 SOEIAJ20 M SUFFIX CASE 967 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. 1 CE 2 O0 3 D0 4 D1 5 O1 6 O2 7 D2 8 D3 9 O3 10 GND DEVICE MARKING INFORMATION See general marking information in the ……
