器件名称:
MC74HC175ADR2
功能描述:
Quad D Flip-Flop with Common Clock and Reset
文件大小:
191.33KB 共8页
简 介:
MC74HC175A Quad D Flip-Flop with Common Clock and Reset High–Performance Silicon–Gate CMOS The MC74HC175A is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of four D flip–flops with common Reset and Clock inputs, and separate D inputs. Reset (active–low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive going edge of the Clock input. http://onsemi.com MARKING DIAGRAMS 16 16 1 PDIP–16 N SUFFIX CASE 648 MC74HC175AN AWLYYWW 1 16 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity 166 FETs or 41.5 Equivalent Gates LOGIC DIAGRAM CLOCK 9 2 3 7 6 10 11 15 14 1 PIN 16 = VCC PIN 8 = GND Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 16 1 SO–16 D SUFFIX CASE 751B 1 HC175A AWLYWW 16 TSSOP–16 DT SUFFIX CASE 948F 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week HC 175A ALYW 16 1 D0 DATA INPUTS D1 4 5 D2 12 D3 13 RESET INVERTING AND NONINVERTING OUTPUTS PIN ASSIGNMENT RESET Q0 Q0 D0 D1 Q1 Q1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC Q3 Q3 D3 D2 Q2 Q2 CLOCK FUNCTION TABLE Inputs Reset L H H H Clock X D X H……
